During the manufacture of semiconductor devices which comprise memory elements, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and some microprocessors, capacitors such as container capacitors and pedestal capacitors are commonly formed. Container and pedestal capacitors are well known to allow an increased stored charge over planar capacitors by increasing the surface area on which the charge may be stored.
FIGS. 1–7 depict a conventional method for forming a plurality of container capacitors from polysilicon. Formation of a pedestal capacitor is similar, but the bottom plate is a solid plug and the cell dielectric and top plate are conformal with the exterior of the bottom plate to form a single-sided vertically-oriented capacitor. FIG. 1 depicts a semiconductor wafer substrate assembly 10 comprising a semiconductor wafer 12 having a plurality of doped source/drain regions 14 within the wafer 12. FIG. 1 further depicts transistors 16 comprising gate oxide 18, a doped polysilicon control gate 20, silicide 22 such as tungsten silicide which increases conductivity of the control gate 20, and a capping layer 24 often manufactured from silicon nitride. Silicon nitride spacers 26 are formed to insulate the control gate 20 and silicide 22 from polysilicon pads 28 to which the container capacitors will be electrically coupled. Shallow trench isolation (STI, field oxide) 30 reduces unwanted electrical interaction between adjacent control gates. An etch stop layer 31 is formed, then a thick layer of deposited oxide 32 such as borophosphosilicate glass (BPSG) formed to provide a base dielectric layer for capacitor features which are formed later. A patterned photoresist layer 34 defines the location of the container capacitors to be formed. The FIG. 1 structure may further include one or more bit (digit) lines under the BPSG layer or various other structural elements or differences which, for simplicity of explanation, have not been depicted.
The FIG. 1 structure is subjected to an anisotropic etch which removes the exposed portions of the BPSG layer to expose the etch stop layer 31 and to form a patterned BPSG layer which provides a base dielectric having recesses for the capacitors. The exposed portion of the etch stop is the removed. Subsequent to the etch of etch stop 31 the polysilicon pads 28 and possibly a portion of capping layer 24 are exposed to result in a structure similar to FIG. 2. The remaining photoresist layer 34 is stripped and any polymer (not depicted) which forms during the etch is removed according to means known in the art to provide the FIG. 3 structure.
As depicted in FIG. 4, a blanket conductive layer 40 such as polysilicon or another material is formed conformal with the deposited oxide layer, and will provide a capacitor storage node for the completed capacitor. A thick blanket filler material 42, such as photoresist, is formed to fill the containers provided by polysilicon 40. The FIG. 4 structure is then subjected to a planarizing process, such as a chemical planarization, a mechanical planarization, or a chemical mechanical planarization (CMP) step. This process removes portions of the photoresist 42, the polysilicon 40, and usually a portion of the BPSG 32 to result in the FIG. 5 structure.
Next, the BPSG 32 is partially etched with an etch selective to polysilicon (i.e. an etch which minimally etches or, preferably, doesn't etch polysilicon) to result in the structure of FIG. 6. At this point in the process the polysilicon storage nodes (capacitor bottom plates) 40 are only minimally supported. The bottom plates 40 in the FIG. 6 structure each comprise a first region 60 which defines a recess, and a second region 62 which defines an opening to the recess, with the first and second regions being continuous, each with the other. In other words, the bottom plate 40 of FIG. 6 defines a receptacle having a rim 62 which defines an opening to the interior of the receptacle. The regions 60, 62 form vertically-oriented sides of the bottom plate, and the sides are electrically-coupled by a horizontally-oriented bottom 64.
Next, a cell dielectric layer 70, for example a layer of high-quality cell nitride, a polysilicon container capacitor top plate 72, and a planar oxide layer such as BPSG 74 are formed according to means known in the art to result in the FIG. 7 structure. This forms a “double-sided” capacitor, as both the capacitor cell dielectric 70 and capacitor top plate 72 follow the contours of the majority of both the inside and outside of each container capacitor bottom plate 40. After forming the structure of FIG. 7, wafer processing continues according to means known in the art.
It can be seen at the FIG. 6 structure that conventional processes remove the oxide 32 which supports the capacitor bottom plate 40. This oxide removal is performed to allow formation of the cell dielectric and capacitor top plate on both sides of the bottom plate to form a double-sided capacitor. The structure of FIG. 6 is easily damaged and susceptible to defects such as leaning (caused, for example, during the etch of BPSG 32 of FIG. 5 to result in FIG. 6), toppling, or lifting of the bottom plate. However, it is desirable to form a double-sided capacitor to increase the cell capacitance which allows the cell height to be decreased over a single sided capacitor. Limiting this vertical dimension of the cell capacitor is desirable because it sets the depth of the contact level to follow. For example, current etch tool technology can etch contacts to a depth of about 3.0 micrometers (μm) to about 3.5 μm. If the capacitor height causes the contact depth to go beyond the 3.0 μm to 3.5 μm limit, then additional masking layers will be needed. One way to do this is to form a portion of the contact to diffusion areas in the wafer before forming the capacitor, then forming the remaining portion after forming the capacitor. Such a process is complex and adds significantly to device cost.
Another problem which can occur during conventional processing results indirectly from the etch of BPSG layer 32 of FIG. 5 to result in the FIG. 6 structure. During this etch, BPSG over the device periphery (not depicted) is also etched, which forms a step in the oxide between the periphery, where there are no cell capacitors, and the array, where the tops of the cell capacitors are at the original level of the top of BPSG 32. After forming the cell dielectric and top plate, the periphery region must be backfilled with oxide, which is then planarized. The requirement to backfill and planarize results in additional processing steps, which contributes to a further increase in costs.
A method used to form a double-sided capacitor such as a container capacitor or a pedestal capacitor which reduces or eliminates one or more the problems described above, and a structure resulting therefrom, would be desirable.